Increases in integration density of semiconductor integrated circuits provides both economic and performance benefit, but also implies extremely fine patterning of the features. In particular, the space between transistor gates has been dramatically reduced with increasing integration density. Consequently, the deposition of dielectric materials for the contact layer becomes more and more challenging in terms of enabling void-free gapfill. This is especially true since the incoming topography from the front-end-of-line (FEoL) processing can have a significant impact on the fill performance of the following layer depositions. With current state-of-the-art deposition processes, e.g., chemical vapor deposition (CVD), it is no longer possible to fill the gaps between the gates. Electrical shorts between adjacent contacts in dense gate structures can be caused by voids in the contact interlayer dielectric (ILD) filled with metal from the contact metallization. Moreover, in cases where the contacts are on different active areas, the electrical short may lead to a failure of the electrical device.
A need therefore exists for methodology reducing the impact of FEoL topography on following layer depositions for dual stress liners.